Every engagement is a version of the same question: this workload has to run in a fixed amount of time, inside a fixed amount of power, on hardware that has already been chosen. What has to change for that to be true?
The answer is almost never a rewrite. It is usually a data layout, a vector kernel, an idle accelerator and a model that was never quantised properly.
Core disciplines
SIMD & NEON optimisation
Hand-tuned Arm NEON and SVE2 intrinsics for the kernels that dominate your profile — convolution, filtering, colour conversion, matrix and FFT work. We fix data layout first, then vectorise, then unroll and software-pipeline against the real issue width of your core.
DSP offload & porting
Moving the heavy loops off the application processor and onto the DSP that is already sitting idle on your SoC. Kernel porting, fixed-point conversion, VLIW scheduling, DMA-driven tiling and the RPC plumbing that keeps the two sides in step.
GPU compute acceleration
OpenCL, Vulkan compute and CUDA kernels written for the memory system you actually have. Workgroup sizing, local-memory tiling, texture paths, zero-copy buffer sharing with the camera and display pipelines, and removal of the hidden synchronisation that stalls mobile GPUs.
Computer-vision engines
Vision pipelines rebuilt end to end: ISP output straight into an accelerated operator graph with no redundant copies, no format churn and a deterministic frame budget. Detection, tracking, stereo depth, OCR, stitching, registration and classical feature work.
Neural-network optimisation
Making a model fit the device instead of asking for a bigger device. Post-training and quantisation-aware INT8/INT4 conversion, structured pruning, operator fusion, graph surgery, knowledge distillation and layer substitution — each step measured against your accuracy floor, not a benchmark set.
Edge AI deployment
Getting the optimised model onto the board and keeping it there: runtime selection, delegate and backend configuration, memory arena planning, multi-model scheduling, OTA-safe model packaging and the regression harness that proves the next model release did not silently regress.
Profiling, power & thermal
Before we change a line of code we build the roofline. Cycle accounting, cache and bandwidth analysis, per-inference energy measurement, DVFS and thermal-throttle behaviour under sustained load — so the number you sign off in the lab is the number you get in the field.
Custom accelerators & RISC-V
When the last factor of two is not in software, we design it in hardware: RISC-V custom instructions, FPGA co-processors, HLS blocks and AXI/DMA data paths, with the driver and runtime that make the accelerator usable from your existing application code.
What a typical engagement produces
Whatever the discipline, the deliverable set looks broadly the same. You should be able to maintain the result without us.
- A measured baseline. The profile of your workload on your board, before anything changed — so every later claim has something to be compared against.
- Optimised source, in your repository. Commented, reviewed, and structured the way your team already works, not dropped in as an opaque binary blob.
- A reference path that still works. Every accelerated path stays switchable against the original, so a regression can be bisected instead of guessed at.
- Accuracy and correctness evidence. Bit-exactness where it is achievable, and a measured delta against your validation set where it is not.
- A sustained-load result. Numbers taken after the board is hot, because that is the number your customer experiences.
- Documentation and a handover session. Why each decision was made, and what to do when the next model or the next SoC arrives.
Method
How the work actually runs.
Measure
We instrument the real workload on the real board. Cycle counts, cache misses, memory bandwidth, thermal headroom and per-stage latency — never a synthetic benchmark. You get the profile even if you stop here.
Model the ceiling
A roofline for each hot stage tells us what is compute-bound, what is bandwidth-bound and what is simply badly scheduled. That is what decides whether the win is in SIMD, in the DSP, on the GPU, or in the data layout.
Re-architect
Layout, tiling and buffer lifetime come before intrinsics. Most of the first big speed-up comes from stopping the copies and giving the vector unit contiguous data to chew on.
Accelerate
Then the hand-written work: NEON/SVE2 kernels, HVX offload, OpenCL or Vulkan compute, quantised graphs and fused operators — each one landed behind a switch so it can be compared against the reference path.
Prove & hand over
Bit-exactness or a stated accuracy delta, a soak test under thermal load, a regression harness wired into your CI, and documentation an engineer on your team can maintain after we leave.
Commercials
Engagement models.
Start small. Almost everyone does.
Fixed-fee audit
A defined scope, a defined price and a written deliverable. Nothing renews automatically and nothing depends on you continuing. It exists so that both sides are arguing about a measured roofline instead of an estimate.
Milestone project
The acceptance criterion — a frame rate, a latency ceiling, a power envelope, a memory footprint — goes into the statement of work before the first commit. Billing follows milestones, so progress and invoices stay in step.
Advisory retainer
A standing block of senior time each month for design reviews, second opinions on a vendor toolchain, and the questions that arrive at short notice during a bring-up. Useful when the need is continuous but not full time.
IP licence & reference designs
Where we already hold an optimised kernel library, a validated model or a reference stack for your silicon, licensing it is faster and cheaper than commissioning the work. Per-product or per-unit terms, with the integration support to make it land.
Send us the hot loop.
A profile, a target board and a number to hit is enough to start a useful conversation.